As a semiconductor device is smaller and highly integrated, the memory capability is increased. However, the high integration of the device increases a chip area but decreases a cell area. The reduction of the cell area decreases an area of a cell capacitor. As a result, the read-out capability of the cell is reduced, the durability is degraded by soft errors of alpha particles, and a sensing margin of a sense amplifier is decreased. Therefore, a method for securing a sufficient capacitance in a limited cell region has been required.
The capacitance refers to a capacity of charges stored in a capacitor. As the capacitance becomes larger, more information can be stored. The capacitance is represented by Equation 1.
                    C        =                  ɛ          ⁢                      A            d                                              Equation        ⁢                                  ⁢        1            
∈ is a dielectric constant determined by kinds of dielectric films disposed between two electrodes, d is a distance between the two electrodes, and A is an effective surface of the two electrodes. Referring to Equation 1, as ∈ is larger, d is shorter between the two electrodes and A of the two electrodes is increased, the capacitance of the capacitor can be increased. The electrode structure of the capacitor is changed to have a three-dimensional type such as a concave structure and a cylinder structure, thereby increasing the effective area of the electrodes.
FIGS. 1a to 1f are cross-sectional views illustrating a conventional method of fabricating a semiconductor device. A buffer oxide film 110, an etch stop film 115, an interlayer insulating film 130, an amorphous carbon layer 140, a silicon nitride oxide film 150 and an anti-reflection film 160 are sequentially formed over a semiconductor substrate 100 including a storage node contact plug 105. A photoresist pattern 170 is formed over anti-reflection film 160 to define a storage node region. Etch stop film 115 includes a nitride film.
Referring to FIG. 1b, anti-reflection film 160 and amorphous carbon layer 140 are sequentially etched using photoresist pattern 170. Interlayer insulating film 130 is etched using the etched silicon nitride oxide film 150 and the etched amorphous carbon layer 140 as an etching mask to form an interlayer insulating pattern 130a that exposes etch stop film 115. Photoresist pattern 170 and anti-reflection film 160 are removed.
Referring to FIGS. 1c and 1d, etch stop film 115 and buffer oxide film 110 are etched using interlayer insulating pattern 130a as an etching mask to form a storage node region 180 exposing storage node contact plug 105. Since buffer oxide film 110 is removed when etch stop film 115 is etched, an over-etching method may be performed. A conductive film 175 is formed over storage node contact plug 105, buffer oxide film 110, etch stop film 115, interlayer insulating pattern 130a, amorphous carbon layer 140 and silicon nitride oxide film 150. Conductive film 175 includes a titanium nitride film.
Referring to FIGS. 1e and 1f, a planarization process is performed on conductive film 175 until interlayer insulating pattern 130a is exposed. A dip-out process is performed to remove interlayer insulating pattern 130a, thereby forming a lower storage node of the cylinder structure.
However, a leaning phenomenon of the lower storage node during the dip-out process occurs by a surface tension of a wet solution, and the lower storage node is pulled out to cause dropping defects, thereby degrading characteristics of the device.